ESP32-S31 Pinout and IO Resource Guide

The ESP32-S31 has 60 physical GPIO pins (GPIO0–GPIO61, except GPIO29 and GPIO41), including 8 low-power (LP) GPIO pins and 52 high-performance (HP) GPIO pins. Each pin can be used as a general-purpose IO or connected to an internal peripheral signal. Through the GPIO matrix and IO MUX, peripheral inputs can be routed from any IO pin and peripheral outputs can be routed to any IO pin. For details, see the ESP32-S31 Technical Reference Manual > IO MUX and GPIO Matrix (GPIO, IO_MUX) PDF.

Quick Start

If you are new to ESP32-S31 development, start with the recommended pin assignments below.

Basic Communication and Control

• UART Pins Allocation — Used for code downloading, log monitoring, and basic serial communication.

  • The ESP32-S31 chip integrates up to 4 main system UARTs and 1 low-power LP UART.

• I2C Pin Allocation — Used for audio codec configuration and data interaction with various low-speed sensors.

  • ESP32-S31 has two HP_I2C bus interfaces and one LP_I2C bus interface. Depending on the configuration, the HP_I2C bus interface can be used in I2C master or slave mode; the LP_I2C bus interface can only be used in I2C master mode. The bus speed can be configured up to 800 Kbit/s in fast mode.

• SPI Pin Allocation — Used for high-speed memory read/write and serial screen control.

  • The ESP32-S31 chip integrates 6 SPI controllers plus 1 low-power SPI (LP SPI), of which:
    • SPI0 and SPI1 are reserved for in-package PSRAM and external flash respectively. By default, they are reserved for system use and cannot be modified by the user.
    • 2 general-purpose SPI controllers are available to users (default: SPI2).
    • 1 low-power SPI controller is available to users (default: LP SPI).

• SDIO Pin Allocation — Used for 4-bit protocol-level transmission of high-speed TF cards and SD devices.

  • The ESP32-S31 chip integrates a high-speed SDIO 3.0 host controller, supporting 1-line and 4-line transmission modes for SD memory cards, SDIO card readers, and SDIO peripherals.

• USB Pin Allocation — Supports USB OTG high-speed bidirectional transmission and USB Serial/JTAG firmware download and debugging.

  • ESP32-S31 supports multiple USB communication interfaces: a USB 2.0 OTG controller supporting full-speed/high-speed modes, and a USB Serial/JTAG debugger supporting program downloading, debugging, and CDC-ACM console.

• Ethernet Pin Allocation — Native 1000 Mbps Gigabit Ethernet MAC, supporting RMII and RGMII.

  • ESP32-S31 natively integrates an IEEE 802.3 compliant Gigabit Media Access Controller (EMAC), supporting Hardware Precision Time Protocol (IEEE 1588-2008 PTP). It provides physical channels for external Ethernet physical layer chips (Ethernet PHY, such as IP101G, RTL8211, etc.), supporting 10/100/1000 Mbps ultra-wide data transmission.

• TWAI Pin Allocation — Used for CAN FD bus automotive and industrial-grade communication.

  • ESP32-S31 supports a TWAI (Two-Wire Automotive Interface) controller, fully compatible with the CAN FD protocol specification, supporting communication rates from 1 Kbit/s to 1 Mbit/s.

• RMT Pin Allocation — Used for infrared codec signal transceiver and driving WS2812 RGB LED strips.

  • The RMT (Remote Control) peripheral of ESP32-S31 supports 4 transmit channels (TX) and 4 receive channels (RX).

• LED PWM Pin Allocation — Pulse Width Modulation (LEDC), used for adjusting LED brightness or controlling motor speed.

  • ESP32-S31 supports 2 groups of LED PWM controllers, with a total of 16 independent PWM generation channels and 4 independent hardware timers, supporting high-precision duty cycles (up to 20-bit) and high-frequency square wave output up to 40 MHz.

• MCPWM Pin Allocation — Dedicated PWM generator for motor control.

  • ESP32-S31 contains a Motor Control Pulse Width Modulator (MCPWM), with a total of 4 MCPWM outputs.

Analog Peripherals

• ADC Pin Allocation — 12-bit high-precision SAR analog-to-digital converter for sampling external analog voltage signals.

  • ESP32-S31 has 2 built-in 12-bit high-resolution Successive Approximation Register analog-to-digital converters (SAR ADC), supporting up to 16 analog measurement input channels, multi-channel continuous scanning, and ultra-high-speed, low-latency data transfer via AXI GDMA.

• DAC Pin Allocation — Hardware digital-to-analog converter, used for outputting analog audio or waveforms.

  • ESP32-S31 has 2 built-in 10-bit and 2 12-bit digital-to-analog conversion controllers (DAC), which can generate smooth analog waveforms or analog audio signals through digital algorithms or look-up tables, with an output range of 0V to 3.3V.

• Touch Pin Allocation — Capacitive touch button, slider, or gesture control detection.

  • ESP32-S31 supports up to 14 highly reliable capacitive touch sensing channels, capable of accurately capturing extremely small capacitance transitions through non-conductive cover plates (such as glass, acrylic, plastic), and supports strict EMC immunity testing.

Multimedia Peripherals

• I2S Pin Allocation — Used to connect audio Codecs for high-quality digital audio capture and output.

  • ESP32-S31 has 2 independent built-in I2S controllers, supporting hardware-level Bluetooth audio (LE Audio) synchronization and APLL high-precision clock source.

• LCD and Camera Pin Allocation — Includes DVP camera, parallel RGB LCD screen.

  • The LCD_CAM controller of ESP32-S31 contains an independent LCD control module and a Camera control module. It can connect external LCD and camera devices with flexible and diverse functions.

System Strapping/Boot Pins

• System Strapping/Boot Pin Allocation — Chip boot mode selection pin definitions.

JTAG Debug Pins

• JTAG Debug Pin Allocation — Used to connect external professional hardware debuggers for advanced debugging.
  • The ESP32-S31 chip integrates two independent JTAG debug physical sources: a built-in USB Serial/JTAG debugger and a standard external physical JTAG interface.

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UART Pin Allocation

1. UART0 Pin Allocation

• UART0 is the default serial console and firmware download interface. During reset and early boot, the chip outputs boot logs on this interface.

2. UART1 ~ UART3 Pin Allocation

• All signal lines of UART1 ~ UART3 support remapping to any idle GPIO via the GPIO matrix feature.

3. LP UART Pin Allocation

• All signal lines of LP UART support remapping to any idle LP GPIO via the GPIO matrix feature. Meanwhile, LP UART also supports allocation using LP IO MUX pins.

  • LP UART IO MUX Pin Allocation

  UART Signal Name	LP IO Name	GPIO Matrix Capability
  LP_UART_DTRN_PAD	LP_GPIO2	Supported
  LP_UART_DTSN_PAD	LP_GPIO3	Supported
  LP_UART_RTSN_PAD	LP_GPIO4	Supported
  LP_UART_CTSN_PAD	LP_GPIO5	Supported
  LP_UART_TXD_PAD	LP_GPIO6	Supported
  LP_UART_RXD_PAD	LP_GPIO7	Supported

[!NOTE]

• In scenarios with long hardware wiring, high-speed transmission (e.g., 3 Mbps), or high-frequency interference, it is recommended to keep traces as short as possible and add impedance matching to ensure absolute stability of serial communication.

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I2C Pin Allocation

1. HP I2C Pin Allocation

• All signal lines of HP I2C support remapping to any idle GPIO via the GPIO matrix feature.

2. LP I2C Pin Allocation

• All signal lines of LP I2C support remapping to any idle LP GPIO via the GPIO matrix feature.

• Meanwhile, LP I2C also supports allocation using LP IO MUX pins. LP I2C IO MUX Pin Allocation:

  Signal Name	LP IO MUX Pin	GPIO Matrix Capability	Direction	Functional Description
  LP_I2C_SDA	LP_GPIO7	Supported	Input/Output	I2C data signal line, requires external 4.7 kΩ pull-up resistor
  LP_I2C_SCL	LP_GPIO6	Supported	Output	I2C clock signal line, requires external 4.7 kΩ pull-up resistor

[!NOTE]

• I2C is an Open-Drain bus. Pull-up resistors (typically 2.2 kΩ to 4.7 kΩ, connected to 3.3V) must be correctly connected on the PCB traces, otherwise it will lead to bus transmission timeouts and unexpected NACK errors.

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SPI Pin Allocation

1. SPI0/1 Flash Pin Allocation

[!NOTE]

• SPI0 and SPI1 interfaces are reserved for Flash use and cannot be used by the user.

2. SPI2 Pin Allocation

General-purpose SPI2 supports remapping to any idle GPIO via the GPIO matrix feature. Meanwhile, general-purpose SPI2 also supports pin allocation via the IO MUX feature to obtain high-speed support.

• HP SPI2 IO MUX Pin Allocation

  • 1-bit HP SPI2 IO MUX Pin Allocation

    SPI Signal Pin	GPIO	GPIO Matrix Capability	Direction	Functional Description
    SPI2_CLK	GPIO20 or GPIO53	Supported	Output	SPI Serial Clock line
    SPI2_D0	GPIO21 or GPIO54	Supported	Input/Output	SPI Data line 0 (MOSI)
    SPI2_D1	GPIO22 or GPIO55	Supported	Input/Output	SPI Data line 1 (MISO)
    SPI2_CS	GPIO23 or GPIO52	Supported	Output (Master) / Input (Slave)	SPI Chip Select signal (CS)
    SPI2_WP	GPIO24 or GPIO56	Supported	Input/Output	Quad SPI Data line D3 (Legacy HOLD)
    SPI2_HD	GPIO25 or GPIO57	Supported	Input/Output	Quad SPI Data line D2 (Legacy WP)

  • 8-bit HP SPI2 IO MUX Pin Allocation

    SPI Signal Pin	GPIO	GPIO Matrix Capability	Direction	Functional Description
    SPI2_CLK	GPIO12	Supported	Output	SPI/OPI Clock signal
    SPI2_CS	GPIO10	Supported	Output	SPI Chip Select signal (CS)
    SPI2_D0	GPIO11	Supported	Input/Output	SPI Data line 0 (MOSI)
    SPI2_D1	GPIO13	Supported	Input/Output	SPI Data line 1 (MISO)
    SPI2_D2	GPIO14	Supported	Input/Output	SPI2 Data line 2 (Quad mode)
    SPI2_D3	GPIO9	Supported	Input/Output	SPI2 Data line 3 (Quad mode)
    SPI2_D4	GPIO15	Supported	Input/Output	SPI2 Data line 4 (Octal mode)
    SPI2_D5	GPIO16	Supported	Input/Output	SPI2 Data line 5 (Octal mode)
    SPI2_D6	GPIO17	Supported	Input/Output	SPI2 Data line 6 (Octal mode)
    SPI2_D7	GPIO18	Supported	Input/Output	SPI2 Data line 7 (Octal mode)
    SPI2_DQS	GPIO19	Supported	Input	Data Strobe signal in SPI2 high-speed DDR/OPI mode, used for synchronous sampling data at the receiving end

3. LP SPI Pin Allocation

• ESP32-S31's LP SPI supports remapping to any idle LP GPIO via the GPIO matrix feature. Meanwhile, LP SPI also supports pin allocation via the IO MUX feature.

  LP SPI IO MUX Pin Allocation

  Signal Name	Recommended Pin	GPIO Matrix Capability	Direction	Functional Description
  LP_SPI_CLK	LP_GPIO2	Supported	Output	SPI Serial Clock line
  LP_SPI_CS	LP_GPIO3	Supported	Input/Output	SPI Chip Select signal (CS)
  LP_SPI_D	LP_GPIO4	Supported	Input/Output	SPI Data line 0 (MOSI)
  LP_SPI_Q	LP_GPIO5	Supported	Input/Output	SPI Data line 1 (MISO)

4. Recommended SPI Pins for Screen Display Control

If your development board is equipped with an LCD screen, its serial control lines typically use the following pins:

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SDIO Pin Allocation

For the SDIO host controller of ESP32-S31, Card 1 can use GPIO20GPIO25 via IO MUX, and Card 2 can use GPIO35GPIO40 via IO MUX. The GPIO matrix feature is not supported.

• SDIO Card 1 IO MUX Pin Allocation

• SDIO Card 2 IO MUX Pin Allocation

[!NOTE]

• SDIO 3.0 supports higher clock frequencies, so high-speed mode has stricter requirements for PCB differential routing and equal-length control. Meanwhile, pull-up resistors of about 10 kΩ are usually required in parallel on the data lines to prevent glitches or packet loss during transmission.

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USB Pin Allocation

1. USB 2.0 HS OTG Pin Allocation

The USB OTG module integrates a built-in high-speed USB 2.0 PHY, which only supports dedicated pins directly connected to the USB Type-A or Type-C physical interface. It does not support the GPIO matrix feature.

2. USB Serial/JTAG Pin Allocation

The USB serial and JTAG debugger use specific IO MUX pins and do not support the GPIO matrix feature.

[!NOTE]

• The dedicated debugger pins GPIO13 and GPIO14 are also alternative pins for the SDIO interface. When SDIO is in 1-bit single-wire mode, the debugger can perfectly share usage with SDIO; however, once the SDIO interface is upgraded to 4-bit mode, the USB Serial/JTAG debug function cannot be used simultaneously.

Ethernet Pin Allocation

The Ethernet pins of ESP32-S31 can only be configured using dedicated high-speed IO MUX pins and do not support the GPIO matrix feature. Users can only choose one of the following two option groups to use, and they cannot be mixed.

[!NOTE]

• Compared to highly sensitive high-speed differential clock and data lines, the signal clock of the Ethernet physical control interface MDIO (Management Data Input/Output) is lower and supports remapping to any general-purpose GPIO pin via the GPIO matrix.

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TWAI Pin Allocation

All signal lines of the TWAI interface of ESP32-S31 support remapping to any idle GPIO via the GPIO matrix feature.

[!NOTE]

• The TWAI chip itself does not integrate a differential physical transceiver, so it is necessary to connect a standard CAN physical transceiver chip (such as TJA1050 or SN65HVD230) in the peripheral circuit design to connect to a real differential two-wire physical CAN bus network segment.

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RMT Pin Allocation

All channel signal lines of RMT support remapping to any idle GPIO via the GPIO matrix feature.

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LED PWM Pin Allocation

All channel signal lines of LEDC PWM support remapping to any idle GPIO via the GPIO matrix feature.

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MCPWM Pin Allocation

The MCPWM pins of ESP32-S31 support remapping to any idle GPIO via the GPIO matrix feature.

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ADC Pin Allocation

All input pins of ESP32-S31 ADC can only be configured via IO MUX pins and do not support the GPIO matrix feature.

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DAC Pin Allocation

All analog signal pins of ESP32-S31's DAC can only be configured via IO MUX pins and do not support the GPIO matrix feature.

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Touch Pin Allocation

• The touch sensor interface of ESP32-S31 is multiplexed with GPIO2GPIO15, LP_GPIO2LP_GPIO15, LP_UART interface, and a set of four-wire interface pins of SPI2. When the analog function is configured to be effective, the digital function multiplexed with it is invalid.
• The touch sensor interface of ESP32-S31 can only be configured via IO MUX pins and does not support the GPIO matrix feature.

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I2S Pin Allocation

The I2S pins of ESP32-S31 support remapping to any idle GPIO via the GPIO matrix feature.

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LCD and Camera Pin Allocation

The CAM and LCD interfaces of the Camera-LCD controller of ESP32-S31 can be configured to use any idle GPIO pins via the GPIO matrix. Meanwhile, LCD and Camera controller pins also support allocation using IO MUX pins.

1. DVP Camera (8-bit Parallel DVP) IO MUX Pin Allocation

2. 16-bit Parallel RGB LCD Screen IO MUX Pin Allocation

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System Strapping/Boot Pin Allocation

During chip power-on reset, the system determines the boot mode of the chip based on the voltage levels of the following specific Strapping pins. Avoid attaching external devices to these pins that would change their initial voltage levels.

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JTAG Debug Pin Allocation

1. Built-in USB Serial/JTAG Debug Pins

• Through the built-in USB physical transceiver, developers only need to use a USB cable directly connected to the chip pins to achieve full-speed JTAG downloading and hardware/software online debugging, without any external debugger (such as J-Link or ESP-Prog).
• USB-JTAG debug pins must strictly be called via IO MUX, remapping via GPIO matrix is not supported:

2. External Physical JTAG Pins (IO MUX)

• If it is necessary to connect an external professional hardware debugger, ESP32-S31 also provides dedicated physical JTAG pins.
• JTAG external physical debug pins are multiplexed with some pins of ADC2 and SPI2, must strictly be configured via IO MUX, remapping via GPIO matrix is not supported:

JTAG Debug Path Selection and Control Mechanism

The switching between built-in USB JTAG and external physical JTAG is jointly controlled by the initial level state of the Strapping pin GPIO37 at the moment of system power-on reset (RST), and the underlying eFuse:

JTAG Path Switching Control Rules

[!NOTE]

• Attention: The default state of GPIO37 at the moment of power-on reset is floating (high impedance). To ensure the system defaults to using the most convenient built-in USB Serial/JTAG debugger after power-on, it is recommended to attach a 10 kΩ pull-down resistor to the GPIO37 pin, or ensure that external circuits will not pull this pin high at the moment of reset, to prevent accidentally switching the debug path to external physical JTAG causing USB debugging to be unavailable.

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Global Physical GPIO and Function Allocation Table

The following table lists pin details. Some GPIOs have usage restrictions; see the notes in the table.